1. Field of the Invention
This invention relates to programmable logic devices (PLDs), and more particularly to a method of implementing multiplexers through the addition of dedicated hardware in a PLD.
2. Description of the Related Art
A PLD is a digital, user-configurable integrated circuit used to implement a custom logic function. For the purposes of this description, the term PLD encompasses any digital logic circuit configured by the end-user, and includes a programmable logic array (“PLA”), a field programmable gate array (“FPGA”), and an erasable and complex PLD. The basic building block of a PLD is a logic element (“LE”). An LE is capable of performing logic functions on a number of input variables. Conventional PLDs combine together multiple LEs through an array of programmable interconnects to facilitate implementation of both simple and complex logic functions.
PLDs are frequently used for a variety of applications which require a large number of multiplexers. The multiplexers are typically implemented within PLDs as “soft” muxes. However, “soft” muxes can consume a large number of LEs within the PLD. For example, two four-input look-up tables (LUTs) are required to implement a simple 4:1 “soft” mux. Two of the inputs to the first LUT are used as multiplexer selection control signals. The third and fourth inputs of the first LUT are used as the first and second multiplexer input signals. The output of the first LUT is connected to an input of the second LUT. One multiplexer selection control signal from the first LUT is connected to an input of the second LUT and the third and fourth inputs of the second LUT are used as the third and fourth multiplexer input signals. Larger multiplexers, such as a 16:1 “soft” mux, require ten four-input LUTs comprising roughly twenty thousand transistors.
Another disadvantage of “soft” muxes within PLDs is that they can be relatively slow. For example, the first and second multiplexer input signals in the 4:1 “soft” mux described above must pass through two levels of logic before a multiplexer output signal is generated. Larger “soft” muxes used to perform wide fan-in multiplexing require some multiplexer input signals to pass through numerous logic levels before generating an output, thus slowing down the speed, efficiency, and economy with which PLDs can perform multiplexing operations. Although synthesis tools can be utilized to rearrange signal paths within a particular LUT, synthesis tools are not sophisticated enough to understand the structure of the overall circuit which is necessary for determining critical paths or rearranging signal paths between different LUTs.
The present invention addresses the above mentioned disadvantages.